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sleep.h

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00001 /* Copyright (c) 2002, 2004 Theodore A. Roth
00002    Copyright (c) 2004, 2007, 2008 Eric B. Weddington
00003    Copyright (c) 2005, 2006, 2007 Joerg Wunsch
00004    All rights reserved.
00005 
00006    Redistribution and use in source and binary forms, with or without
00007    modification, are permitted provided that the following conditions are met:
00008 
00009    * Redistributions of source code must retain the above copyright
00010      notice, this list of conditions and the following disclaimer.
00011 
00012    * Redistributions in binary form must reproduce the above copyright
00013      notice, this list of conditions and the following disclaimer in
00014      the documentation and/or other materials provided with the
00015      distribution.
00016 
00017    * Neither the name of the copyright holders nor the names of
00018      contributors may be used to endorse or promote products derived
00019      from this software without specific prior written permission.
00020 
00021    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00022    AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00023    IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
00024    ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
00025    LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
00026    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
00027    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
00028    INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
00029    CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
00030    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
00031    POSSIBILITY OF SUCH DAMAGE. */
00032 
00033 /* $Id$ */
00034 
00035 #ifndef _AVR_SLEEP_H_
00036 #define _AVR_SLEEP_H_ 1
00037 
00038 #include <avr/io.h>
00039 #include <stdint.h>
00040 
00041 
00042 /** \file */
00043 
00044 /** \defgroup avr_sleep <avr/sleep.h>: Power Management and Sleep Modes
00045 
00046     \code #include <avr/sleep.h>\endcode
00047 
00048     Use of the \c SLEEP instruction can allow an application to reduce its
00049     power comsumption considerably. AVR devices can be put into different
00050     sleep modes. Refer to the datasheet for the details relating to the device
00051     you are using.
00052 
00053     There are several macros provided in this header file to actually
00054     put the device into sleep mode.  The simplest way is to optionally
00055     set the desired sleep mode using \c set_sleep_mode() (it usually
00056     defaults to idle mode where the CPU is put on sleep but all
00057     peripheral clocks are still running), and then call
00058     \c sleep_mode(). This macro automatically sets the sleep enable bit, goes 
00059     to sleep, and clears the sleep enable bit.
00060     
00061     Example:
00062     \code
00063     #include <avr/sleep.h>
00064 
00065     ...
00066       set_sleep_mode(<mode>);
00067       sleep_mode();
00068     \endcode
00069     
00070     Note that unless your purpose is to completely lock the CPU (until a 
00071     hardware reset), interrupts need to be enabled before going to sleep.
00072 
00073     As the \c sleep_mode() macro might cause race conditions in some
00074     situations, the individual steps of manipulating the sleep enable
00075     (SE) bit, and actually issuing the \c SLEEP instruction, are provided
00076     in the macros \c sleep_enable(), \c sleep_disable(), and
00077     \c sleep_cpu().  This also allows for test-and-sleep scenarios that
00078     take care of not missing the interrupt that will awake the device
00079     from sleep.
00080 
00081     Example:
00082     \code
00083     #include <avr/interrupt.h>
00084     #include <avr/sleep.h>
00085 
00086     ...
00087       set_sleep_mode(<mode>);
00088       cli();
00089       if (some_condition)
00090       {
00091         sleep_enable();
00092         sei();
00093         sleep_cpu();
00094         sleep_disable();
00095       }
00096       sei();
00097     \endcode
00098 
00099     This sequence ensures an atomic test of \c some_condition with
00100     interrupts being disabled.  If the condition is met, sleep mode
00101     will be prepared, and the \c SLEEP instruction will be scheduled
00102     immediately after an \c SEI instruction.  As the intruction right
00103     after the \c SEI is guaranteed to be executed before an interrupt
00104     could trigger, it is sure the device will really be put to sleep.
00105 
00106     Some devices have the ability to disable the Brown Out Detector (BOD) before 
00107     going to sleep. This will also reduce power while sleeping. If the
00108     specific AVR device has this ability then an additional macro is defined:
00109     \c sleep_bod_disable(). This macro generates inlined assembly code
00110     that will correctly implement the timed sequence for disabling the BOD
00111     before sleeping. However, there is a limited number of cycles after the
00112     BOD has been disabled that the device can be put into sleep mode, otherwise
00113     the BOD will not truly be disabled. Recommended practice is to disable
00114     the BOD (\c sleep_bod_disable()), set the interrupts (\c sei()), and then
00115     put the device to sleep (\c sleep_cpu()), like so:
00116 
00117     \code
00118     #include <avr/interrupt.h>
00119     #include <avr/sleep.h>
00120 
00121     ...
00122       set_sleep_mode(<mode>);
00123       cli();
00124       if (some_condition)
00125       {
00126         sleep_enable();
00127         sleep_bod_disable();
00128         sei();
00129         sleep_cpu();
00130         sleep_disable();
00131       }
00132       sei();
00133     \endcode
00134 */
00135 
00136 
00137 /* Define an internal sleep control register and an internal sleep enable bit mask. */
00138 #if defined(SLEEP_CTRL)
00139 
00140     /* XMEGA devices */
00141     #define _SLEEP_CONTROL_REG  SLEEP_CTRL
00142     #define _SLEEP_ENABLE_MASK  SLEEP_SEN_bm
00143 
00144 #elif defined(SMCR)
00145 
00146     #define _SLEEP_CONTROL_REG  SMCR
00147     #define _SLEEP_ENABLE_MASK  _BV(SE)
00148 
00149 #elif defined(__AVR_AT94K__)
00150 
00151     #define _SLEEP_CONTROL_REG  MCUR
00152     #define _SLEEP_ENABLE_MASK  _BV(SE)
00153 
00154 #else
00155 
00156     #define _SLEEP_CONTROL_REG  MCUCR
00157     #define _SLEEP_ENABLE_MASK  _BV(SE)
00158 
00159 #endif
00160 
00161 
00162 /* Define set_sleep_mode() and sleep mode values per device. */
00163 #if defined(__AVR_ATmega161__)
00164 
00165     #define SLEEP_MODE_IDLE         0
00166     #define SLEEP_MODE_PWR_DOWN     1
00167     #define SLEEP_MODE_PWR_SAVE     2
00168 
00169     #define set_sleep_mode(mode) \
00170     do { \
00171         MCUCR = ((MCUCR & ~_BV(SM1)) | ((mode) == SLEEP_MODE_PWR_DOWN || (mode) == SLEEP_MODE_PWR_SAVE ? _BV(SM1) : 0)); \
00172         EMCUCR = ((EMCUCR & ~_BV(SM0)) | ((mode) == SLEEP_MODE_PWR_SAVE ? _BV(SM0) : 0)); \
00173     } while(0)
00174 
00175 
00176 #elif defined(__AVR_ATmega162__) \
00177 || defined(__AVR_ATmega8515__)
00178 
00179     #define SLEEP_MODE_IDLE         0
00180     #define SLEEP_MODE_PWR_DOWN     1
00181     #define SLEEP_MODE_PWR_SAVE     2
00182     #define SLEEP_MODE_ADC          3
00183     #define SLEEP_MODE_STANDBY      4
00184     #define SLEEP_MODE_EXT_STANDBY  5
00185 
00186     #define set_sleep_mode(mode) \
00187     do { \
00188         MCUCR = ((MCUCR & ~_BV(SM1)) | ((mode) == SLEEP_MODE_IDLE ? 0 : _BV(SM1))); \
00189         MCUCSR = ((MCUCSR & ~_BV(SM2)) | ((mode) == SLEEP_MODE_STANDBY  || (mode) == SLEEP_MODE_EXT_STANDBY ? _BV(SM2) : 0)); \
00190         EMCUCR = ((EMCUCR & ~_BV(SM0)) | ((mode) == SLEEP_MODE_PWR_SAVE || (mode) == SLEEP_MODE_EXT_STANDBY ? _BV(SM0) : 0)); \
00191     } while(0)
00192 
00193 #elif defined(__AVR_AT90S2313__) \
00194 || defined(__AVR_AT90S2323__) \
00195 || defined(__AVR_AT90S2333__) \
00196 || defined(__AVR_AT90S2343__) \
00197 || defined(__AVR_AT43USB320__) \
00198 || defined(__AVR_AT43USB355__) \
00199 || defined(__AVR_AT90S4414__) \
00200 || defined(__AVR_AT90S4433__) \
00201 || defined(__AVR_AT90S8515__) \
00202 || defined(__AVR_ATtiny22__)
00203 
00204     #define SLEEP_MODE_IDLE         0
00205     #define SLEEP_MODE_PWR_DOWN     _BV(SM)
00206 
00207     #define set_sleep_mode(mode) \
00208     do { \
00209         _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~_BV(SM)) | (mode)); \
00210     } while(0)
00211 
00212 #elif defined(__AVR_ATA6616C__) \
00213 || defined(__AVR_ATA6617C__) \
00214 || defined(__AVR_ATA664251__) \
00215 || defined(__AVR_ATtiny167__) \
00216 || defined(__AVR_ATtiny87__) \
00217 || defined(__AVR_ATtiny441__) \
00218 || defined(__AVR_ATtiny828__) \
00219 || defined(__AVR_ATtiny841__)
00220 
00221     #define SLEEP_MODE_IDLE         0
00222     #define SLEEP_MODE_ADC          _BV(SM0)
00223     #define SLEEP_MODE_PWR_DOWN     _BV(SM1)
00224 
00225     #define set_sleep_mode(mode) \
00226     do { \
00227         _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
00228     } while(0)
00229 
00230 #elif defined(__AVR_AT90S4434__) \
00231 || defined(__AVR_ATA5505__) \
00232 || defined(__AVR_ATA5272__) \
00233 || defined(__AVR_AT76C711__) \
00234 || defined(__AVR_AT90S8535__) \
00235 || defined(__AVR_ATmega103__) \
00236 || defined(__AVR_ATmega161__) \
00237 || defined(__AVR_ATmega163__) \
00238 || defined(__AVR_ATmega16HVB__) \
00239 || defined(__AVR_ATmega16HVBrevB__) \
00240 || defined(__AVR_ATmega32HVB__) \
00241 || defined(__AVR_ATmega32HVBrevB__) \
00242 || defined(__AVR_ATtiny13__) \
00243 || defined(__AVR_ATtiny13A__) \
00244 || defined(__AVR_ATtiny15__) \
00245 || defined(__AVR_ATtiny24__) \
00246 || defined(__AVR_ATtiny24A__) \
00247 || defined(__AVR_ATtiny44__) \
00248 || defined(__AVR_ATtiny44A__) \
00249 || defined(__AVR_ATtiny84__) \
00250 || defined(__AVR_ATtiny84A__) \
00251 || defined(__AVR_ATtiny25__) \
00252 || defined(__AVR_ATtiny45__) \
00253 || defined(__AVR_ATtiny48__) \
00254 || defined(__AVR_ATtiny85__) \
00255 || defined(__AVR_ATtiny88__)
00256 
00257     #define SLEEP_MODE_IDLE         0
00258     #define SLEEP_MODE_ADC          _BV(SM0)
00259     #define SLEEP_MODE_PWR_DOWN     _BV(SM1)
00260     #define SLEEP_MODE_PWR_SAVE     (_BV(SM0) | _BV(SM1))
00261 
00262     #define set_sleep_mode(mode) \
00263     do { \
00264         _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
00265     } while(0)
00266 
00267 #elif defined(__AVR_ATmega16HVA__) \
00268 || defined(__AVR_ATmega8HVA__) 
00269 
00270     #define SLEEP_MODE_IDLE         (0)
00271     #define SLEEP_MODE_ADC          _BV(SM0)
00272     #define SLEEP_MODE_PWR_SAVE     (_BV(SM0) | _BV(SM1))
00273     #define SLEEP_MODE_PWR_OFF      _BV(SM2)
00274 
00275 
00276     #define set_sleep_mode(mode) \
00277     do { \
00278         _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
00279     } while(0)
00280 
00281 #elif defined(__AVR_ATmega406__)
00282 
00283     #define SLEEP_MODE_IDLE         (0)
00284     #define SLEEP_MODE_ADC          _BV(SM0)
00285     #define SLEEP_MODE_PWR_DOWN     _BV(SM1)
00286     #define SLEEP_MODE_PWR_SAVE     (_BV(SM0) | _BV(SM1))
00287     #define SLEEP_MODE_PWR_OFF      _BV(SM2)
00288 
00289     #define set_sleep_mode(mode) \
00290     do { \
00291         _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
00292     } while(0)
00293 
00294 #elif defined(__AVR_ATtiny2313__) \
00295 || defined(__AVR_ATtiny2313A__) \
00296 || defined(__AVR_ATtiny4313__)
00297 
00298     #define SLEEP_MODE_IDLE         0
00299     #define SLEEP_MODE_PWR_DOWN     (_BV(SM0) | _BV(SM1))
00300     #define SLEEP_MODE_STANDBY      _BV(SM1)
00301 
00302     #define set_sleep_mode(mode) \
00303     do { \
00304         _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
00305     } while(0)
00306 
00307 #elif defined(__AVR_AT94K__) \
00308 || defined(__AVR_ATmega64HVE__) \
00309 || defined(__AVR_ATmega64HVE2__)
00310 
00311     #define SLEEP_MODE_IDLE         0
00312     #define SLEEP_MODE_PWR_DOWN     _BV(SM1)
00313     #define SLEEP_MODE_PWR_SAVE     (_BV(SM0) | _BV(SM1))
00314 
00315     #define set_sleep_mode(mode) \
00316     do { \
00317         _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
00318     } while(0)
00319 
00320 #elif defined(__AVR_ATtiny26__) \
00321 || defined(__AVR_ATtiny261__) \
00322 || defined(__AVR_ATtiny261A__) \
00323 || defined(__AVR_ATtiny461__) \
00324 || defined(__AVR_ATtiny461A__) \
00325 || defined(__AVR_ATtiny861__) \
00326 || defined(__AVR_ATtiny861A__) \
00327 || defined(__AVR_ATtiny43U__) \
00328 || defined(__AVR_ATtiny1634__)
00329 
00330     #define SLEEP_MODE_IDLE         0
00331     #define SLEEP_MODE_ADC          _BV(SM0)
00332     #define SLEEP_MODE_PWR_DOWN     _BV(SM1)
00333     #define SLEEP_MODE_STANDBY      (_BV(SM0) | _BV(SM1))
00334 
00335     #define set_sleep_mode(mode) \
00336     do { \
00337         _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
00338     } while(0)
00339 
00340 #elif defined(__AVR_AT90PWM216__) \
00341 || defined(__AVR_AT90PWM316__) \
00342 || defined(__AVR_AT90PWM161__) \
00343 || defined(__AVR_AT90PWM81__) \
00344 || defined(__AVR_AT90PWM1__) \
00345 || defined(__AVR_AT90PWM2__) \
00346 || defined(__AVR_AT90PWM2B__) \
00347 || defined(__AVR_AT90PWM3__) \
00348 || defined(__AVR_AT90PWM3B__) \
00349 || defined(__AVR_ATmega32M1__) \
00350 || defined(__AVR_ATmega16M1__) \
00351 || defined(__AVR_ATmega64M1__) 
00352 
00353     #define SLEEP_MODE_IDLE         0
00354     #define SLEEP_MODE_ADC          _BV(SM0)
00355     #define SLEEP_MODE_PWR_DOWN     _BV(SM1)
00356     #define SLEEP_MODE_STANDBY      (_BV(SM1) | _BV(SM2))
00357 
00358     #define set_sleep_mode(mode) \
00359     do { \
00360         _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
00361     } while(0)
00362 
00363 #elif defined(__AVR_AT90USB1286__) \
00364 || defined(__AVR_AT90USB1287__) \
00365 || defined(__AVR_AT90USB646__) \
00366 || defined(__AVR_AT90USB647__) \
00367 || defined(__AVR_ATA6614Q__) \
00368 || defined(__AVR_ATmega128__) \
00369 || defined(__AVR_ATmega128A__) \
00370 || defined(__AVR_ATmega1280__) \
00371 || defined(__AVR_ATmega1281__) \
00372 || defined(__AVR_ATmega1284__) \
00373 || defined(__AVR_ATmega1284P__) \
00374 || defined(__AVR_ATmega128RFA1__) \
00375 || defined(__AVR_ATmega128RFR2__) \
00376 || defined(__AVR_ATmega1284RFR2__) \
00377 || defined(__AVR_ATmega16__) \
00378 || defined(__AVR_ATmega16A__) \
00379 || defined(__AVR_ATmega162__) \
00380 || defined(__AVR_ATmega164A__) \
00381 || defined(__AVR_ATmega164P__) \
00382 || defined(__AVR_ATmega164PA__) \
00383 || defined(__AVR_ATmega168A__) \
00384 || defined(__AVR_ATmega168P__) \
00385 || defined(__AVR_ATmega168PA__) \
00386 || defined(__AVR_ATmega16HVA2__) \
00387 || defined(__AVR_ATmega16U4__) \
00388 || defined(__AVR_ATmega2560__) \
00389 || defined(__AVR_ATmega2561__) \
00390 || defined(__AVR_ATmega256RFR2__) \
00391 || defined(__AVR_ATmega2564RFR2__) \
00392 || defined(__AVR_ATmega32__) \
00393 || defined(__AVR_ATmega32A__) \
00394 || defined(__AVR_ATmega323__) \
00395 || defined(__AVR_ATmega324A__) \
00396 || defined(__AVR_ATmega324P__) \
00397 || defined(__AVR_ATmega324PA__) \
00398 || defined(__AVR_ATmega328__) \
00399 || defined(__AVR_ATmega328P__) \
00400 || defined(__AVR_ATmega32C1__) \
00401 || defined(__AVR_ATmega32U4__) \
00402 || defined(__AVR_ATmega32U6__) \
00403 || defined(__AVR_ATmega48A__) \
00404 || defined(__AVR_ATmega48PA__) \
00405 || defined(__AVR_ATmega48P__) \
00406 || defined(__AVR_ATmega64__) \
00407 || defined(__AVR_ATmega64A__) \
00408 || defined(__AVR_ATmega640__) \
00409 || defined(__AVR_ATmega644__) \
00410 || defined(__AVR_ATmega644A__) \
00411 || defined(__AVR_ATmega644P__) \
00412 || defined(__AVR_ATmega644PA__) \
00413 || defined(__AVR_ATmega64C1__) \
00414 || defined(__AVR_ATmega64RFR2__) \
00415 || defined(__AVR_ATmega644RFR2__) \
00416 || defined(__AVR_ATmega8515__) \
00417 || defined(__AVR_ATmega8535__) \
00418 || defined(__AVR_ATmega88A__) \
00419 || defined(__AVR_ATmega88P__) \
00420 || defined(__AVR_ATmega88PA__) 
00421 
00422     #define SLEEP_MODE_IDLE         (0)
00423     #define SLEEP_MODE_ADC          _BV(SM0)
00424     #define SLEEP_MODE_PWR_DOWN     _BV(SM1)
00425     #define SLEEP_MODE_PWR_SAVE     (_BV(SM0) | _BV(SM1))
00426     #define SLEEP_MODE_STANDBY      (_BV(SM1) | _BV(SM2))
00427     #define SLEEP_MODE_EXT_STANDBY  (_BV(SM0) | _BV(SM1) | _BV(SM2))
00428 
00429 
00430     #define set_sleep_mode(mode) \
00431     do { \
00432         _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
00433     } while(0)
00434 
00435 #elif defined(__AVR_ATmega8A__) \
00436 || defined(__AVR_ATmega8__) \
00437 || defined(__AVR_ATmega6450A__) \
00438 || defined(__AVR_ATmega6450P__) \
00439 || defined(__AVR_ATmega645A__) \
00440 || defined(__AVR_ATmega645P__) \
00441 || defined(__AVR_ATmega3250A__) \
00442 || defined(__AVR_ATmega3250PA__) \
00443 || defined(__AVR_ATmega325A__) \
00444 || defined(__AVR_ATmega325PA__) \
00445 || defined(__AVR_ATmega165A__) \
00446 || defined(__AVR_ATmega165P__) \
00447 || defined(__AVR_ATmega165PA__) \
00448 || defined(__AVR_ATmega169A__) \
00449 || defined(__AVR_ATmega169P__) \
00450 || defined(__AVR_ATmega169PA__) \
00451 || defined(__AVR_ATmega329A__) \
00452 || defined(__AVR_ATmega329PA__) \
00453 || defined(__AVR_ATmega3290A__) \
00454 || defined(__AVR_ATmega3290PA__) \
00455 || defined(__AVR_ATmega649A__) \
00456 || defined(__AVR_ATmega649P__) \
00457 || defined(__AVR_ATmega6490A__) \
00458 || defined(__AVR_ATmega6490P__) \
00459 || defined(__AVR_ATmega165__) \
00460 || defined(__AVR_ATmega169__) \
00461 || defined(__AVR_ATmega48__) \
00462 || defined(__AVR_ATmega88__) \
00463 || defined(__AVR_ATmega168__) \
00464 || defined(__AVR_ATmega325P__) \
00465 || defined(__AVR_ATmega3250P__) \
00466 || defined(__AVR_ATmega325__) \
00467 || defined(__AVR_ATmega3250__) \
00468 || defined(__AVR_ATmega645__) \
00469 || defined(__AVR_ATmega6450__) \
00470 || defined(__AVR_ATmega329__) \
00471 || defined(__AVR_ATmega329P__) \
00472 || defined(__AVR_ATmega3290__) \
00473 || defined(__AVR_ATmega3290P__) \
00474 || defined(__AVR_ATmega649__) \
00475 || defined(__AVR_ATmega6490__) \
00476 || defined(__AVR_AT90CAN128__) \
00477 || defined(__AVR_AT90CAN32__) \
00478 || defined(__AVR_AT90CAN64__) \
00479 || defined(__AVR_ATA6612C__) \
00480 || defined(__AVR_ATA6613C__) 
00481 
00482     #define SLEEP_MODE_IDLE         (0)
00483     #define SLEEP_MODE_ADC          _BV(SM0)
00484     #define SLEEP_MODE_PWR_DOWN     _BV(SM1)
00485     #define SLEEP_MODE_PWR_SAVE     (_BV(SM0) | _BV(SM1))
00486     #define SLEEP_MODE_STANDBY      (_BV(SM1) | _BV(SM2))
00487 
00488 
00489     #define set_sleep_mode(mode) \
00490     do { \
00491         _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
00492     } while(0)
00493 
00494 #elif defined(__AVR_ATxmega16A4__) \
00495 || defined(__AVR_ATxmega16A4U__) \
00496 || defined(__AVR_ATxmega16C4__) \
00497 || defined(__AVR_ATxmega16D4__) \
00498 || defined(__AVR_ATxmega32A4__) \
00499 || defined(__AVR_ATxmega32A4U__) \
00500 || defined(__AVR_ATxmega32C3__) \
00501 || defined(__AVR_ATxmega32C4__) \
00502 || defined(__AVR_ATxmega32D3__) \
00503 || defined(__AVR_ATxmega32D4__) \
00504 || defined(__AVR_ATxmega8E5__) \
00505 || defined(__AVR_ATxmega16E5__) \
00506 || defined(__AVR_ATxmega32E5__) \
00507 || defined(__AVR_ATxmega64A1__) \
00508 || defined(__AVR_ATxmega64A1U__) \
00509 || defined(__AVR_ATxmega64A3__) \
00510 || defined(__AVR_ATxmega64A3U__) \
00511 || defined(__AVR_ATxmega64A4U__) \
00512 || defined(__AVR_ATxmega64B1__) \
00513 || defined(__AVR_ATxmega64B3__) \
00514 || defined(__AVR_ATxmega64C3__) \
00515 || defined(__AVR_ATxmega64D3__) \
00516 || defined(__AVR_ATxmega64D4__) \
00517 || defined(__AVR_ATxmega128A1__) \
00518 || defined(__AVR_ATxmega128A1U__) \
00519 || defined(__AVR_ATxmega128A3__) \
00520 || defined(__AVR_ATxmega128A3U__) \
00521 || defined(__AVR_ATxmega128A4U__) \
00522 || defined(__AVR_ATxmega128B1__) \
00523 || defined(__AVR_ATxmega128B3__) \
00524 || defined(__AVR_ATxmega128C3__) \
00525 || defined(__AVR_ATxmega128D3__) \
00526 || defined(__AVR_ATxmega128D4__) \
00527 || defined(__AVR_ATxmega192A3__) \
00528 || defined(__AVR_ATxmega192A3U__) \
00529 || defined(__AVR_ATxmega192C3__) \
00530 || defined(__AVR_ATxmega192D3__) \
00531 || defined(__AVR_ATxmega256A3__) \
00532 || defined(__AVR_ATxmega256A3U__) \
00533 || defined(__AVR_ATxmega256C3__) \
00534 || defined(__AVR_ATxmega256D3__) \
00535 || defined(__AVR_ATxmega256A3B__) \
00536 || defined(__AVR_ATxmega256A3BU__) \
00537 || defined(__AVR_ATxmega384C3__) \
00538 || defined(__AVR_ATxmega384D3__)
00539 
00540     #define SLEEP_MODE_IDLE         (0)
00541     #define SLEEP_MODE_PWR_DOWN     (SLEEP_SMODE1_bm)
00542     #define SLEEP_MODE_PWR_SAVE     (SLEEP_SMODE1_bm | SLEEP_SMODE0_bm)
00543     #define SLEEP_MODE_STANDBY      (SLEEP_SMODE2_bm | SLEEP_SMODE1_bm)
00544     #define SLEEP_MODE_EXT_STANDBY  (SLEEP_SMODE2_bm | SLEEP_SMODE1_bm | SLEEP_SMODE0_bm)
00545 
00546     #define set_sleep_mode(mode) \
00547     do { \
00548         _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(SLEEP_SMODE2_bm | SLEEP_SMODE1_bm | SLEEP_SMODE0_bm)) | (mode)); \
00549     } while(0)
00550 
00551 #elif defined(__AVR_AT90SCR100__) \
00552 || defined(__AVR_ATmega8U2__) \
00553 || defined(__AVR_ATmega16U2__) \
00554 || defined(__AVR_ATmega32U2__) \
00555 || defined(__AVR_AT90USB162__) \
00556 || defined(__AVR_AT90USB82__) 
00557 
00558     #define SLEEP_MODE_IDLE         (0)
00559     #define SLEEP_MODE_PWR_DOWN     _BV(SM1)
00560     #define SLEEP_MODE_PWR_SAVE     (_BV(SM0) | _BV(SM1))
00561     #define SLEEP_MODE_STANDBY      (_BV(SM1) | _BV(SM2))
00562     #define SLEEP_MODE_EXT_STANDBY  (_BV(SM0) | _BV(SM1) | _BV(SM2))
00563 
00564     #define set_sleep_mode(mode) \
00565     do { \
00566         _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
00567     } while(0)
00568 
00569 #elif defined(__AVR_ATA6285__) \
00570 || defined(__AVR_ATA6286__) \
00571 || defined(__AVR_ATA6289__)
00572 
00573     #define SLEEP_MODE_IDLE                     (0)
00574     #define SLEEP_MODE_SENSOR_NOISE_REDUCTION   (_BV(SM0))
00575     #define SLEEP_MODE_PWR_DOWN                 (_BV(SM1))
00576 
00577     #define set_sleep_mode(mode) \
00578     do { \
00579         _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
00580     } while(0)
00581 
00582 #elif defined (__AVR_ATA5790__) \
00583 || defined (__AVR_ATA5790N__) \
00584 || defined (__AVR_ATA5795__) \
00585 || defined (__AVR_ATA5782__) \
00586 || defined (__AVR_ATA5831__)
00587 
00588     #define SLEEP_MODE_IDLE           (0)
00589     #define SLEEP_MODE_EXT_PWR_SAVE   (_BV(SM0))
00590     #define SLEEP_MODE_PWR_DOWN       (_BV(SM1))
00591     #define SLEEP_MODE_PWR_SAVE       (_BV(SM1) | _BV(SM0))     
00592     
00593     #define set_sleep_mode(mode) \
00594     do { \
00595         _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
00596     } while(0)
00597 
00598 #elif defined (__AVR_ATA5702M322__) 
00599 
00600     #define SLEEP_MODE_IDLE           (0)
00601     #define SLEEP_MODE_EXT_PWR_SAVE   (_BV(SM0))
00602     #define SLEEP_MODE_PWR_DOWN       (_BV(SM1))
00603     #define SLEEP_MODE_PWR_SAVE       (_BV(SM1) | _BV(SM0))     
00604     #define SLEEP_MODE_EXT_PWR_DOWN   (_BV(SM2))
00605     #define SLEEP_MODE_PWR_OFF        (_BV(SM2) | _BV(SM0))
00606     
00607     #define set_sleep_mode(mode) \
00608     do { \
00609         _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
00610     } while(0)
00611 
00612 #elif defined(__AVR_ATtiny4__) \
00613 || defined(__AVR_ATtiny5__) \
00614 || defined(__AVR_ATtiny9__) \
00615 || defined(__AVR_ATtiny10__) \
00616 || defined(__AVR_ATtiny20__) \
00617 || defined(__AVR_ATtiny40__)
00618 
00619     #define SLEEP_MODE_IDLE         0
00620     #define SLEEP_MODE_ADC          _BV(SM0)
00621     #define SLEEP_MODE_PWR_DOWN     _BV(SM1)
00622     #define SLEEP_MODE_STANDBY      _BV(SM2)
00623 
00624     #define set_sleep_mode(mode) \
00625     do { \
00626         _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
00627     } while(0)
00628 
00629 #else
00630 
00631     #error "No SLEEP mode defined for this device."
00632 
00633 #endif
00634 
00635 
00636 
00637 /** \ingroup avr_sleep
00638 
00639     Put the device in sleep mode. How the device is brought out of sleep mode
00640     depends on the specific mode selected with the set_sleep_mode() function.
00641     See the data sheet for your device for more details. */
00642 
00643 
00644 #if defined(__DOXYGEN__)
00645 
00646 /** \ingroup avr_sleep
00647 
00648     Set the SE (sleep enable) bit.
00649 */
00650 extern void sleep_enable (void);
00651 
00652 #else
00653 
00654 #define sleep_enable()             \
00655 do {                               \
00656   _SLEEP_CONTROL_REG |= (uint8_t)_SLEEP_ENABLE_MASK;   \
00657 } while(0)
00658 
00659 #endif
00660 
00661 
00662 #if defined(__DOXYGEN__)
00663 
00664 /** \ingroup avr_sleep
00665 
00666     Clear the SE (sleep enable) bit.
00667 */
00668 extern void sleep_disable (void);
00669 
00670 #else
00671 
00672 #define sleep_disable()            \
00673 do {                               \
00674   _SLEEP_CONTROL_REG &= (uint8_t)(~_SLEEP_ENABLE_MASK);  \
00675 } while(0)
00676 
00677 #endif
00678 
00679 
00680 /** \ingroup avr_sleep
00681 
00682     Put the device into sleep mode.  The SE bit must be set
00683     beforehand, and it is recommended to clear it afterwards.
00684 */
00685 #if defined(__DOXYGEN__)
00686 
00687 extern void sleep_cpu (void);
00688 
00689 #else
00690 
00691 #define sleep_cpu()                              \
00692 do {                                             \
00693   __asm__ __volatile__ ( "sleep" "\n\t" :: );    \
00694 } while(0)
00695 
00696 #endif
00697 
00698 
00699 #if defined(__DOXYGEN__)
00700 
00701 extern void sleep_mode (void);
00702 
00703 #else
00704 
00705 #define sleep_mode() \
00706 do {                 \
00707     sleep_enable();  \
00708     sleep_cpu();     \
00709     sleep_disable(); \
00710 } while (0)
00711 
00712 #endif
00713 
00714 
00715 #if defined(__DOXYGEN__)
00716 
00717 extern void sleep_bod_disable (void);
00718 
00719 #else
00720 
00721 #if defined(BODS) && defined(BODSE)
00722 
00723 #ifdef BODCR
00724 
00725 #define BOD_CONTROL_REG BODCR
00726 
00727 #else
00728 
00729 #define BOD_CONTROL_REG MCUCR
00730 
00731 #endif
00732 
00733 #define sleep_bod_disable() \
00734 do { \
00735   uint8_t tempreg; \
00736   __asm__ __volatile__("in %[tempreg], %[mcucr]" "\n\t" \
00737                        "ori %[tempreg], %[bods_bodse]" "\n\t" \
00738                        "out %[mcucr], %[tempreg]" "\n\t" \
00739                        "andi %[tempreg], %[not_bodse]" "\n\t" \
00740                        "out %[mcucr], %[tempreg]" \
00741                        : [tempreg] "=&d" (tempreg) \
00742                        : [mcucr] "I" _SFR_IO_ADDR(BOD_CONTROL_REG), \
00743                          [bods_bodse] "i" (_BV(BODS) | _BV(BODSE)), \
00744                          [not_bodse] "i" (~_BV(BODSE))); \
00745 } while (0)
00746 
00747 #endif
00748 
00749 #endif
00750 
00751 
00752 /*@}*/
00753 
00754 #endif /* _AVR_SLEEP_H_ */

Automatically generated by Doxygen 1.6.1 on 25 Apr 2014.