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00031 #ifndef _AVR_BOOT_H_
00032 #define _AVR_BOOT_H_ 1
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00104 #include <avr/eeprom.h>
00105 #include <avr/io.h>
00106 #include <inttypes.h>
00107 #include <limits.h>
00108
00109
00110 #if defined (SPMCSR)
00111 # define __SPM_REG SPMCSR
00112 #else
00113 # if defined (SPMCR)
00114 # define __SPM_REG SPMCR
00115 # else
00116 # error AVR processor does not provide bootloader support!
00117 # endif
00118 #endif
00119
00120
00121
00122 #if defined(SPMEN)
00123 # define __SPM_ENABLE SPMEN
00124 #elif defined(SELFPRGEN)
00125 # define __SPM_ENABLE SELFPRGEN
00126 #else
00127 # error Cannot find SPM Enable bit definition!
00128 #endif
00129
00130
00131
00132
00133
00134
00135
00136
00137
00138 #define BOOTLOADER_SECTION __attribute__ ((section (".bootloader")))
00139
00140
00141 #ifdef ASB
00142 #define __COMMON_ASB ASB
00143 #else
00144 #define __COMMON_ASB RWWSB
00145 #endif
00146
00147 #ifdef ASRE
00148 #define __COMMON_ASRE ASRE
00149 #else
00150 #define __COMMON_ASRE RWWSRE
00151 #endif
00152
00153
00154
00155 #define BLB12 5
00156 #define BLB11 4
00157 #define BLB02 3
00158 #define BLB01 2
00159
00160
00161
00162
00163
00164 #define boot_spm_interrupt_enable() (__SPM_REG |= (uint8_t)_BV(SPMIE))
00165
00166
00167
00168
00169
00170 #define boot_spm_interrupt_disable() (__SPM_REG &= (uint8_t)~_BV(SPMIE))
00171
00172
00173
00174
00175
00176 #define boot_is_spm_interrupt() (__SPM_REG & (uint8_t)_BV(SPMIE))
00177
00178
00179
00180
00181
00182 #define boot_rww_busy() (__SPM_REG & (uint8_t)_BV(__COMMON_ASB))
00183
00184
00185
00186
00187
00188 #define boot_spm_busy() (__SPM_REG & (uint8_t)_BV(__SPM_ENABLE))
00189
00190
00191
00192
00193
00194 #define boot_spm_busy_wait() do{}while(boot_spm_busy())
00195
00196 #define __BOOT_PAGE_ERASE (_BV(__SPM_ENABLE) | _BV(PGERS))
00197 #define __BOOT_PAGE_WRITE (_BV(__SPM_ENABLE) | _BV(PGWRT))
00198 #define __BOOT_PAGE_FILL _BV(__SPM_ENABLE)
00199 #define __BOOT_RWW_ENABLE (_BV(__SPM_ENABLE) | _BV(__COMMON_ASRE))
00200 #if defined(BLBSET)
00201 #define __BOOT_LOCK_BITS_SET (_BV(__SPM_ENABLE) | _BV(BLBSET))
00202 #elif defined(RFLB)
00203 #define __BOOT_LOCK_BITS_SET (_BV(__SPM_ENABLE) | _BV(RFLB))
00204 #endif
00205
00206 #define __boot_page_fill_normal(address, data) \
00207 (__extension__({ \
00208 __asm__ __volatile__ \
00209 ( \
00210 "movw r0, %3\n\t" \
00211 "sts %0, %1\n\t" \
00212 "spm\n\t" \
00213 "clr r1\n\t" \
00214 : \
00215 : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
00216 "r" ((uint8_t)(__BOOT_PAGE_FILL)), \
00217 "z" ((uint16_t)(address)), \
00218 "r" ((uint16_t)(data)) \
00219 : "r0" \
00220 ); \
00221 }))
00222
00223 #define __boot_page_fill_alternate(address, data)\
00224 (__extension__({ \
00225 __asm__ __volatile__ \
00226 ( \
00227 "movw r0, %3\n\t" \
00228 "sts %0, %1\n\t" \
00229 "spm\n\t" \
00230 ".word 0xffff\n\t" \
00231 "nop\n\t" \
00232 "clr r1\n\t" \
00233 : \
00234 : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
00235 "r" ((uint8_t)(__BOOT_PAGE_FILL)), \
00236 "z" ((uint16_t)(address)), \
00237 "r" ((uint16_t)(data)) \
00238 : "r0" \
00239 ); \
00240 }))
00241
00242 #define __boot_page_fill_extended(address, data) \
00243 (__extension__({ \
00244 __asm__ __volatile__ \
00245 ( \
00246 "movw r0, %4\n\t" \
00247 "movw r30, %A3\n\t" \
00248 "sts %1, %C3\n\t" \
00249 "sts %0, %2\n\t" \
00250 "spm\n\t" \
00251 "clr r1\n\t" \
00252 : \
00253 : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
00254 "i" (_SFR_MEM_ADDR(RAMPZ)), \
00255 "r" ((uint8_t)(__BOOT_PAGE_FILL)), \
00256 "r" ((uint32_t)(address)), \
00257 "r" ((uint16_t)(data)) \
00258 : "r0", "r30", "r31" \
00259 ); \
00260 }))
00261
00262 #define __boot_page_erase_normal(address) \
00263 (__extension__({ \
00264 __asm__ __volatile__ \
00265 ( \
00266 "sts %0, %1\n\t" \
00267 "spm\n\t" \
00268 : \
00269 : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
00270 "r" ((uint8_t)(__BOOT_PAGE_ERASE)), \
00271 "z" ((uint16_t)(address)) \
00272 ); \
00273 }))
00274
00275 #define __boot_page_erase_alternate(address) \
00276 (__extension__({ \
00277 __asm__ __volatile__ \
00278 ( \
00279 "sts %0, %1\n\t" \
00280 "spm\n\t" \
00281 ".word 0xffff\n\t" \
00282 "nop\n\t" \
00283 : \
00284 : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
00285 "r" ((uint8_t)(__BOOT_PAGE_ERASE)), \
00286 "z" ((uint16_t)(address)) \
00287 ); \
00288 }))
00289
00290 #define __boot_page_erase_extended(address) \
00291 (__extension__({ \
00292 __asm__ __volatile__ \
00293 ( \
00294 "movw r30, %A3\n\t" \
00295 "sts %1, %C3\n\t" \
00296 "sts %0, %2\n\t" \
00297 "spm\n\t" \
00298 : \
00299 : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
00300 "i" (_SFR_MEM_ADDR(RAMPZ)), \
00301 "r" ((uint8_t)(__BOOT_PAGE_ERASE)), \
00302 "r" ((uint32_t)(address)) \
00303 : "r30", "r31" \
00304 ); \
00305 }))
00306
00307 #define __boot_page_write_normal(address) \
00308 (__extension__({ \
00309 __asm__ __volatile__ \
00310 ( \
00311 "sts %0, %1\n\t" \
00312 "spm\n\t" \
00313 : \
00314 : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
00315 "r" ((uint8_t)(__BOOT_PAGE_WRITE)), \
00316 "z" ((uint16_t)(address)) \
00317 ); \
00318 }))
00319
00320 #define __boot_page_write_alternate(address) \
00321 (__extension__({ \
00322 __asm__ __volatile__ \
00323 ( \
00324 "sts %0, %1\n\t" \
00325 "spm\n\t" \
00326 ".word 0xffff\n\t" \
00327 "nop\n\t" \
00328 : \
00329 : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
00330 "r" ((uint8_t)(__BOOT_PAGE_WRITE)), \
00331 "z" ((uint16_t)(address)) \
00332 ); \
00333 }))
00334
00335 #define __boot_page_write_extended(address) \
00336 (__extension__({ \
00337 __asm__ __volatile__ \
00338 ( \
00339 "movw r30, %A3\n\t" \
00340 "sts %1, %C3\n\t" \
00341 "sts %0, %2\n\t" \
00342 "spm\n\t" \
00343 : \
00344 : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
00345 "i" (_SFR_MEM_ADDR(RAMPZ)), \
00346 "r" ((uint8_t)(__BOOT_PAGE_WRITE)), \
00347 "r" ((uint32_t)(address)) \
00348 : "r30", "r31" \
00349 ); \
00350 }))
00351
00352 #define __boot_rww_enable() \
00353 (__extension__({ \
00354 __asm__ __volatile__ \
00355 ( \
00356 "sts %0, %1\n\t" \
00357 "spm\n\t" \
00358 : \
00359 : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
00360 "r" ((uint8_t)(__BOOT_RWW_ENABLE)) \
00361 ); \
00362 }))
00363
00364 #define __boot_rww_enable_alternate() \
00365 (__extension__({ \
00366 __asm__ __volatile__ \
00367 ( \
00368 "sts %0, %1\n\t" \
00369 "spm\n\t" \
00370 ".word 0xffff\n\t" \
00371 "nop\n\t" \
00372 : \
00373 : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
00374 "r" ((uint8_t)(__BOOT_RWW_ENABLE)) \
00375 ); \
00376 }))
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00394
00395 #define __boot_lock_bits_set(lock_bits) \
00396 (__extension__({ \
00397 uint8_t value = (uint8_t)(~(lock_bits)); \
00398 __asm__ __volatile__ \
00399 ( \
00400 "ldi r30, 1\n\t" \
00401 "ldi r31, 0\n\t" \
00402 "mov r0, %2\n\t" \
00403 "sts %0, %1\n\t" \
00404 "spm\n\t" \
00405 : \
00406 : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
00407 "r" ((uint8_t)(__BOOT_LOCK_BITS_SET)), \
00408 "r" (value) \
00409 : "r0", "r30", "r31" \
00410 ); \
00411 }))
00412
00413 #define __boot_lock_bits_set_alternate(lock_bits) \
00414 (__extension__({ \
00415 uint8_t value = (uint8_t)(~(lock_bits)); \
00416 __asm__ __volatile__ \
00417 ( \
00418 "ldi r30, 1\n\t" \
00419 "ldi r31, 0\n\t" \
00420 "mov r0, %2\n\t" \
00421 "sts %0, %1\n\t" \
00422 "spm\n\t" \
00423 ".word 0xffff\n\t" \
00424 "nop\n\t" \
00425 : \
00426 : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
00427 "r" ((uint8_t)(__BOOT_LOCK_BITS_SET)), \
00428 "r" (value) \
00429 : "r0", "r30", "r31" \
00430 ); \
00431 }))
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00455
00456 #define GET_LOW_FUSE_BITS (0x0000)
00457
00458
00459
00460
00461 #define GET_LOCK_BITS (0x0001)
00462
00463
00464
00465
00466 #define GET_EXTENDED_FUSE_BITS (0x0002)
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00471 #define GET_HIGH_FUSE_BITS (0x0003)
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00484
00485 #define boot_lock_fuse_bits_get(address) \
00486 (__extension__({ \
00487 uint8_t __result; \
00488 __asm__ __volatile__ \
00489 ( \
00490 "sts %1, %2\n\t" \
00491 "lpm %0, Z\n\t" \
00492 : "=r" (__result) \
00493 : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
00494 "r" ((uint8_t)(__BOOT_LOCK_BITS_SET)), \
00495 "z" ((uint16_t)(address)) \
00496 ); \
00497 __result; \
00498 }))
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00510
00511 #define __BOOT_SIGROW_READ (_BV(__SPM_ENABLE) | _BV(SIGRD))
00512
00513 #define boot_signature_byte_get(addr) \
00514 (__extension__({ \
00515 uint8_t __result; \
00516 __asm__ __volatile__ \
00517 ( \
00518 "sts %1, %2\n\t" \
00519 "lpm %0, Z" "\n\t" \
00520 : "=r" (__result) \
00521 : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
00522 "r" ((uint8_t)(__BOOT_SIGROW_READ)), \
00523 "z" ((uint16_t)(addr)) \
00524 ); \
00525 __result; \
00526 }))
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00589 #if defined(__AVR_ATmega161__) || defined(__AVR_ATmega163__) \
00590 || defined(__AVR_ATmega323__)
00591
00592
00593 #define boot_page_fill(address, data) __boot_page_fill_alternate(address, data)
00594 #define boot_page_erase(address) __boot_page_erase_alternate(address)
00595 #define boot_page_write(address) __boot_page_write_alternate(address)
00596 #define boot_rww_enable() __boot_rww_enable_alternate()
00597 #define boot_lock_bits_set(lock_bits) __boot_lock_bits_set_alternate(lock_bits)
00598
00599 #elif (FLASHEND > USHRT_MAX)
00600
00601
00602 #define boot_page_fill(address, data) __boot_page_fill_extended(address, data)
00603 #define boot_page_erase(address) __boot_page_erase_extended(address)
00604 #define boot_page_write(address) __boot_page_write_extended(address)
00605 #define boot_rww_enable() __boot_rww_enable()
00606 #define boot_lock_bits_set(lock_bits) __boot_lock_bits_set(lock_bits)
00607
00608 #else
00609
00610
00611 #define boot_page_fill(address, data) __boot_page_fill_normal(address, data)
00612 #define boot_page_erase(address) __boot_page_erase_normal(address)
00613 #define boot_page_write(address) __boot_page_write_normal(address)
00614 #define boot_rww_enable() __boot_rww_enable()
00615 #define boot_lock_bits_set(lock_bits) __boot_lock_bits_set(lock_bits)
00616
00617 #endif
00618
00619
00620
00621
00622
00623
00624 #define boot_page_fill_safe(address, data) \
00625 do { \
00626 boot_spm_busy_wait(); \
00627 eeprom_busy_wait(); \
00628 boot_page_fill(address, data); \
00629 } while (0)
00630
00631
00632
00633
00634
00635
00636 #define boot_page_erase_safe(address) \
00637 do { \
00638 boot_spm_busy_wait(); \
00639 eeprom_busy_wait(); \
00640 boot_page_erase (address); \
00641 } while (0)
00642
00643
00644
00645
00646
00647
00648 #define boot_page_write_safe(address) \
00649 do { \
00650 boot_spm_busy_wait(); \
00651 eeprom_busy_wait(); \
00652 boot_page_write (address); \
00653 } while (0)
00654
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00659
00660 #define boot_rww_enable_safe() \
00661 do { \
00662 boot_spm_busy_wait(); \
00663 eeprom_busy_wait(); \
00664 boot_rww_enable(); \
00665 } while (0)
00666
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00670
00671
00672 #define boot_lock_bits_set_safe(lock_bits) \
00673 do { \
00674 boot_spm_busy_wait(); \
00675 eeprom_busy_wait(); \
00676 boot_lock_bits_set (lock_bits); \
00677 } while (0)
00678
00679 #endif